1. Field of the Invention
The present invention relates to a general purpose register or memory array having devices for testing the memory cells.
2. Description of the Related Art
Memory arrays, like other electronic circuit components, are susceptible to manufacturing defects and failure. Memory arrays are typically fabricated on an integrated circuit chip, which may be a dedicated memory chip or may include other circuit components. Defects in a memory array may be caused by fabrication errors or improper handling. Environmental factors, age or improper use can cause a memory array to fail at any time.
The susceptibility of memory arrays to manufacturing defects and failure has prompted the development of means for testing them. One such means, which is sometimes referred to as functional testing, involves writing one or more data patterns to the memory array, then reading the data patterns from the memory array, and comparing the patterns written to the patterns read. A discrepancy indicates a defect or failure. Such functional testing has the advantage of requiring no components dedicated to the testing function to be included in the chip. An additional advantage is that each bit can be tested independently. The primary disadvantage of functional testing is that it is relatively slow, since the chip is operated in its normal manner over the entire memory array. Furthermore, the read port circuitry is not tested independently of the write port circuitry. Isolating the cause of the discrepancy between the data written and the data read may be impossible because the discrepancy could have been caused by the write port, the read port, the memory cell storage element, or a combination of these components.
Another testing means involves incorporating into the chip built-in-self-test (BIST) circuitry. A BIST is thorough because it tests each and every memory cell. Such testing granularity is highly desirable. A BIST can also test a memory array reasonably rapidly because it exercises the memory cells directly. The primary disadvantage of BIST is that its components take up a significant amount of space or real-estate on the chip. The extra components also undesirably increase signal loading.
It would be desirable to provide a memory array testing device and method that includes some of the advantages of both BIST testing and functional pattern testing. These problems are satisfied by the present invention in the manner described below.